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Derginin Adı:
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Mediterranean Journal of Modeling and Simulation
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Cilt:
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2019/1
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Sayı:
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1
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Makale Başlık:
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Efficient Absolute Difference Circuit for SAD computation on FPGA
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Makale Alternatif Dilde Başlık:
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Alternatif dilde başlık bulunmamaktadır. There is no article title in another language.)
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Makale Eklenme Tarihi:
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8.10.2019
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Okunma Sayısı:
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1
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Makale Özeti:
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Video Compression is very essential to meet the technological demands such as low power, less memory and fast transfer rate for different range of devices and for various multimedia applications. Video compression is primarily achieved by Motion Estimation (ME) process in any video encoder which contributes to significant compression gain. Sum of Absolute Difference (SAD) is used as distortion metric in ME process. In this paper, efficient Absolute Difference(AD) circuit is proposed which uses Brent Kung Adder(BKA) and a comparator based on modified 1's complement principle and conditional sum adder scheme. Results shows that proposed architecture reduces delay by 15% and number of slice LUTs by 42 % as compared to conventional architecture. Simulation and synthesis are done on Xilinx ISE 14.2 using Virtex 7 FPGA.
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Alternatif Dilde Özet:
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Alternatif dilde abstract bulunmamaktadır. (There is no abstract in another language.)
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